Senior Staff Design Verification Engineer – PCIe/CXL Sub-System

Job Title

Senior Staff Design Verification Engineer – PCIe/CXL Sub-System

Role Summary

Lead verification efforts for PCIe and CXL subsystems within Marvell's Center of Excellence, delivering production-ready IP building blocks for data center SoCs. The role covers test planning, UVM/SystemVerilog testbench architecture, VIP integration, performance validation, and cross-functional collaboration with design, architecture, firmware, and validation teams.

Experience Level

Senior-level. The posting requests approximately 5–10 years of ASIC/SoC verification experience.

Responsibilities

Primary responsibilities include verification planning, testbench development, and signoff for PCIe/CXL subsystems:

• Own end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems from test planning to coverage closure and signoff.
• Define and execute comprehensive verification plans derived from protocol specs and micro-architecture requirements.
• Architect and develop scalable UVM/SystemVerilog testbenches for controllers and fabric-level subsystems.
• Integrate and configure PCIe/CXL VIP for subsystem and system-level verification.
• Validate CXL.io, CXL.cache, and CXL.mem protocols including coherency and memory semantics across complex flows.
• Develop constrained-random and directed test suites to achieve functional and corner-case coverage.
• Debug protocol violations, ordering issues, and coherency bugs using waveforms, logs, and protocol analyzers.
• Implement SystemVerilog Assertions (SVA) and drive functional, code, and assertion coverage closure.
• Validate performance metrics (latency, throughput, QoS) under high-bandwidth and stress workloads.
• Develop automation (Python/Shell) for regression management, log triage, and coverage reporting.
• Collaborate with design, architecture, firmware, and validation teams and mentor junior engineers; support emulation/FPGA validation and post-silicon bring-up where applicable.

Requirements

Must-have technical skills and experience (concise):

• 5–10 years of ASIC/SoC verification experience focused on high-speed interfaces.
• Strong knowledge of PCIe and CXL protocols and architecture.
• Expertise in SystemVerilog and UVM methodology.
• Proven ability to debug complex verification issues and identify root causes.
• Familiarity with industry-standard simulation, waveform debugging, and coverage tools.
• Solid understanding of digital design fundamentals.

Nice-to-have:

• Assertion-based verification (SVA).
• Performance modeling and traffic generation experience.
• Exposure to emulation platforms (Palladium, Veloce) and FPGA-based validation.
• Scripting skills (Python/Perl/Shell) for automation.
• Experience with low-power verification (UPF).

Education Requirements

Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

Compensation note: Expected base pay range listed by employer: $135,900 - $201,130 per year.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.