Senior Staff Design Verification Engineer – Memory Sub-System (LPDDR/DDR/HBM)

Job Title

Senior Staff Design Verification Engineer – Memory Sub-System (LPDDR/DDR/HBM)

Role Summary

Senior verification engineer in the Center of Excellence (Custom Compute and Storage, Data Center Group) responsible for verification of memory IP subsystems used in Marvell SoCs. The role focuses on developing and executing verification plans, building UVM/SystemVerilog environments, and working with design, architecture, and firmware teams to deliver production-ready memory controllers and PHY interfaces.

Experience Level

Senior-level. The posting requests approximately 5–10 years of ASIC/SoC verification experience.

Responsibilities

Primary responsibilities include planning and executing verification for high-speed memory interfaces and collaborating across design and validation teams.

• Develop and execute verification plans for DDR4/DDR5, LPDDR4/LPDDR5, and HBM2/HBM3 interfaces.
• Design and maintain UVM/SystemVerilog-based verification environments, testbenches, sequences, and checkers.
• Perform protocol-level verification for memory controllers and PHY interfaces; implement coverage-driven verification.
• Analyze and debug simulation failures, identify root causes, and drive resolution with design and firmware teams.
• Work toward coverage closure (functional, code, and assertion coverage) and ensure spec compliance.
• Support emulation/FPGA validation and post-silicon bring-up as needed.
• Review design specifications and provide feedback for testability and robustness.

Requirements

Key must-have skills and technologies followed by preferred (nice-to-have) items.

• Must-have: Proven ASIC/SoC verification experience using SystemVerilog and UVM methodology.
• Must-have: Strong knowledge of DDR, LPDDR, or HBM protocols and architecture.
• Must-have: Experience debugging complex verification issues and using industry-standard simulation, waveform, and coverage tools.
• Must-have: Solid understanding of digital design fundamentals.
• Nice-to-have: Knowledge of JEDEC standards for DDR/LPDDR/HBM and assertion-based verification (SVA).
• Nice-to-have: Experience with performance modeling/traffic generation, emulation platforms (e.g., Palladium, Veloce), scripting (Python/Perl/Shell), and low-power verification (UPF).

Education Requirements

Bachelor's or master’s degree in Electrical Engineering, Computer Engineering, or a related technical field (the posting specifies these degrees). No other certifications were specified.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.