Senior Staff Design Verification Engineer – Memory Sub-System (DDR/LPDDR/HBM)

Job Title

Senior Staff Design Verification Engineer – Memory Sub-System (DDR/LPDDR/HBM)

Role Summary

Senior verification engineer in the Center of Excellence (Custom Compute and Storage business unit) responsible for verification of high-speed memory subsystems (DDR/LPDDR/HBM) used in Marvell SoCs. The role collaborates with RTL design, architecture, firmware, and silicon validation teams to deliver production-ready IP subsystems.

Focus areas include protocol-level verification, UVM/SystemVerilog environment development, coverage-driven verification, and debugging to enable first-pass-right silicon.

Experience Level

Senior-level. The posting requests approximately 5–10 years of ASIC/SoC verification experience.

Responsibilities

Deliver and execute verification for memory controller and PHY interfaces and drive closure across teams.

• Develop and execute verification plans for DDR4/DDR5, LPDDR4/LPDDR5, and HBM2/HBM3 interfaces.
• Design and maintain UVM/SystemVerilog verification environments, testbenches, sequences, and checkers.
• Perform protocol-level verification of memory controllers and PHY interfaces and validate performance targets.
• Implement coverage-driven verification: functional, code, and assertion coverage collection and analysis.
• Analyze and debug simulation failures, identify root causes, and drive fixes with design and firmware teams.
• Support emulation/FPGA validation and post-silicon bring-up where applicable.
• Review design specifications and provide feedback for testability and robustness.

Requirements

Key technical skills and experience required or strongly preferred.

• Must-have: 5–10 years of ASIC/SoC verification experience focused on memory interfaces.
• Must-have: Strong knowledge of DDR, LPDDR, or HBM protocols and architecture.
• Must-have: Expertise in SystemVerilog and UVM methodology.
• Must-have: Experience debugging complex verification issues and using simulation, waveform, and coverage tools.
• Must-have: Solid understanding of digital design fundamentals.
• Preferred: Knowledge of JEDEC standards for DDR/LPDDR/HBM and assertion-based verification (SVA).
• Preferred: Experience with performance modeling, traffic generation, and emulation platforms (e.g., Palladium, Veloce).
• Preferred: Scripting skills (Python, Perl, Shell) and exposure to low-power verification (UPF).

Education Requirements

Bachelor's or master’s degree in Electrical Engineering, Computer Engineering, or a related field is requested by the posting.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.