Senior Staff Design Verification Engineer – Memory Sub-System

Job Title

Senior Staff Design Verification Engineer – Memory Sub-System

Role Summary

Join the Center of Excellence within Marvell's Custom Compute and Storage business to design and verify memory subsystem IP used in high-performance SoCs for cloud, AI, and data-center customers. The role focuses on verification of high-speed memory interfaces and delivering production-ready IP subsystems.

Experience Level

Senior-level role. Preferred experience: 5–10 years in ASIC/SoC verification; senior responsibilities in verification architecture and cross-functional technical leadership.

Responsibilities

Core verification and collaboration responsibilities include:

• Develop and execute verification plans for high-speed memory interfaces (DDR4/DDR5, LPDDR4/LPDDR5, HBM2/HBM3).
• Build and enhance UVM/SystemVerilog-based verification environments.
• Develop testbenches, sequences, checkers, and assertions for functional and performance validation.
• Perform protocol-level verification of memory controllers and PHY interfaces.
• Analyze and debug simulation failures, identify root causes, and drive resolution.
• Work closely with design, architecture, and firmware teams to ensure coverage closure and spec compliance.
• Contribute to coverage-driven verification (functional, code, and assertion coverage).
• Support emulation/FPGA validation and post-silicon bring-up (preferred but not mandatory).
• Review design specifications and provide feedback for testability and robustness.

Requirements

Minimum and preferred technical qualifications.

• Must-have: 5–10 years of ASIC/SoC verification experience.
• Must-have: Strong knowledge of DDR/LPDDR/HBM protocols and architecture.
• Must-have: Expertise in SystemVerilog and UVM methodology.
• Must-have: Experience debugging complex verification issues and using simulation/waveform/coverage tools.
• Must-have: Solid understanding of digital design fundamentals.
• Must-have: Ability to collaborate across design, architecture, firmware, and validation teams.
• Must-have: Eligibility to access export-controlled technology as required by U.S. export laws.

Nice-to-have:

• Knowledge of JEDEC standards for DDR/LPDDR/HBM.
• Experience with assertion-based verification (SVA).
• Performance modeling and traffic generation experience.
• Experience with emulation platforms (e.g., Palladium, Veloce).
• Scripting skills (Python, Perl, Shell).
• Experience with low-power verification (UPF/CPF).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.