Senior Staff Design Engineer - PCIE/CXL Subsystem COE

Job Title

Senior Staff Design Engineer - PCIE/CXL Subsystem COE

Role Summary

Lead the micro-architecture, RTL implementation, and integration of PCIe/CXL IP subsystems for Marvell's Center of Excellence (COE). The role spans architecture, RTL design, verification, physical design/DFT coordination, and silicon bring-up for data-center and cloud SoCs.

Work cross-functionally to deliver production-ready, reusable subsystem IP that meets performance, interoperability, and sign-off requirements.

Experience Level

Senior — typically requires 10+ years of relevant RTL design experience (per employer guidance).

Responsibilities

Primary responsibilities include defining and delivering PCIe/CXL subsystem IP and supporting integration through silicon validation.

• Own PCIE/CXL subsystem micro-architecture, RTL design, and integration into SoCs.
• Translate architecture requirements into robust, PD- and DFT-friendly RTL.
• Collaborate with design verification on test plans, debug, and coverage closure.
• Work with Physical Design and DFT teams to meet synthesis and sign-off goals.
• Support silicon bring-up, post-silicon debug, and collaborate with firmware/validation teams.
• Drive code quality, design reuse, and best practices; participate in design and milestone reviews.
• Mentor and provide technical leadership to junior designers.

Requirements

Must-have technical skills and tools experience. Nice-to-have items are listed separately.

• Proven track record delivering complex PCIe/CXL controllers or subsystems from architecture to RTL closure.
• Strong hands-on RTL development in SystemVerilog / Verilog.
• Familiarity with PCIe and CXL specifications and implementation details.
• Experience integrating ARM-based SoCs and AMBA protocols (AXI-4, CHI, ACE).
• Deep understanding of clocking/resets, CDC/RDC issues, low-power techniques, and performance optimization.
• Experience with lint, CDC/RDC analysis, synthesis flows, and design sign-off processes.
• Familiarity with industry EDA tools (Synopsys, Cadence, Mentor/Siemens) and version control systems (GIT, SVN).
• Proficient scripting skills (TCL, Perl, Python) for automation and flows.
• Interview integrity: employer disallows use of AI tools during interviews; candidates should be prepared for real-time evaluation.

Nice-to-have:

• End-to-end PCIe/CXL subsystem RTL execution and sign-off experience.
• Design experience for high-performance, low-latency datapaths, ordering/coherency, and error handling.
• Post-silicon bring-up and debug collaboration experience with firmware/validation teams.
• Prior experience mentoring engineers and providing cross-functional technical leadership.

Education Requirements

Master's or Bachelor's degree in Electronics/Electrical Engineering (explicit). The posting indicates a Master's/Bachelor's in Electronics/Electrical Engineering and expects about 10+ years of relevant RTL design experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.