Senior Staff Applications Engineer – Physical Design (Synthesis)

Job Title

Senior Staff Applications Engineer – Physical Design (Synthesis)

Role Summary

Customer-facing applications engineer responsible for diagnosing and resolving complex issues across the RTL-to-GDSII flow, deploying tool releases and methodologies at customer sites, and collaborating with R&D and Sales to deliver production-ready solutions. The role focuses on enabling timing closure, power optimization, and signoff on advanced-node designs.

Experience Level

Senior — typically requires 8+ years of relevant experience (6+ years with an advanced degree) in ASIC implementation, physical design, or a closely related domain.

Responsibilities

Primary responsibilities involve on-site and remote technical support, methodology deployment, and cross-team collaboration to ensure customer tapeouts succeed.

• Diagnose and resolve complex issues across the RTL-to-GDSII flow on live customer designs using tools such as Fusion Compiler, IC Compiler II, PrimeTime, and StarRC.
• Deploy new product releases and advanced-node methodologies at customer sites; train design teams on implementation, timing-closure, and power-optimization techniques.
• Reproduce customer-reported bugs, validate fixes with R&D, and provide actionable feedback to influence the product roadmap.
• Review customer methodologies and recommend synthesis strategies, floorplanning approaches, CTS optimization, and signoff practices.
• Scope and support proof-of-concept engagements with Sales and technical leads to evaluate design challenges and demonstrate solutions.
• Automate workflows and debug processes using scripting (Perl, Tcl, Python) to increase customer productivity and replicate complex scenarios.
• Present technical findings, trade-offs, and product capabilities to engineering teams and management.

Requirements

Core technical skills and behaviors required for successful performance in the role.

• Must-have: Hands-on experience across the full RTL-to-GDSII flow: synthesis, place-and-route, static timing analysis, power analysis, and physical verification.
• Must-have: Working knowledge of Synopsys toolset such as Fusion Compiler, Design Compiler, IC Compiler II, PrimeTime, StarRC, Formality, or ICC2.
• Must-have: Deep understanding of advanced-node design challenges (FinFET effects, multi-patterning, electromigration, sub-10nm timing closure techniques).
• Must-have: Proficiency scripting in Perl, Tcl, or Python to automate workflows, parse logs, and build custom analysis.
• Must-have: Strong verbal and written communication skills; able to explain timing paths and tool behavior to engineers and management.
• Must-have: Ability to reproduce issues, escalate effectively, and work directly with R&D under time pressure.
• Must-have: Willingness to travel occasionally for deployments, training, and escalations.
• Nice-to-have: Experience in ASIC implementation areas beyond physical design (RTL coding, verification, formal checking).

Education Requirements

Typically requires a bachelor’s degree and a minimum of 8 years of related experience, or an advanced degree and a minimum of 6 years of related experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.