Senior Physical Design Engineer – DPG Layout

Job Title

Senior Physical Design Engineer – DPG Layout

Role Summary

Implement and sign off block-level physical design for complex SoC blocks and large digital sub-blocks. Work within the physical design (PD) team and with STA, RTL, CAD/methodology, and integration teams to meet power, performance, and area (PPA) targets through floorplanning, placement, clocking, routing, and optimization.

Experience Level

Senior — typically 6+ years of hands-on physical design experience for complex SoCs or large digital blocks.

Responsibilities

Lead and execute block-level physical implementation and signoff activities; collaborate across design and tool teams to resolve issues and support tape-out.

• Perform floorplanning, placement, clock tree synthesis (CTS), routing, and physical optimizations to meet PPA targets.
• Drive block-level timing closure (setup/hold) across multi-mode, multi-corner (MMMC) scenarios in coordination with STA and RTL teams.
• Implement and validate clocking, reset, and power intent (UPF/CPF) for assigned blocks.
• Execute physical verification and signoff checks (DRC/LVS, antenna, IR drop, EM, noise, timing) and resolve violations.
• Support tape-out activities: ECO implementation, closure tracking, signoff reviews, and documentation.
• Collaborate with CAD, methodology, and technology teams to debug PD tool or flow issues and adopt approved methodologies for advanced nodes.
• Develop scripts and automation to improve productivity and turnaround time.
• Participate in design reviews and post-silicon debug when required, correlating layout/timing/power analysis with silicon observations.

Requirements

Must-have technical skills and practical experience for immediate contribution; items listed as "nice-to-have" when indicated.

• 6+ years of hands-on physical design implementation for complex SoCs or large digital blocks.
• Proven experience with block-level timing analysis and closure, including MMMC setup and hold closure.
• Experience on advanced process nodes (e.g., 7nm, 5nm, or equivalent) and familiarity with node-dependent PD challenges.
• Proficiency with industry-standard P&R tools such as Cadence Innovus and/or Synopsys IC Compiler II.
• Hands-on experience with physical verification and signoff, including DRC, LVS, antenna, and foundry checks.
• Working knowledge of power integrity and reliability analysis (IR drop, EM, noise, crosstalk).
• Solid understanding of digital design fundamentals to collaborate effectively with RTL and architecture teams.
• Scripting/automation skills (Tcl, Python, or similar) for flow improvements and debugging.
• Ability to mentor junior engineers on block ownership, PD flows, and best practices.
• Nice-to-have: exposure to AI-assisted tools or data-driven techniques for debugging or flow efficiency.

Education Requirements

B.Tech in Electronics, Electronics & Communication, or VLSI Engineering (or equivalent practical experience); M.Tech in VLSI Design, Microelectronics, or Electronics Engineering was also listed as a qualification. Equivalent industry experience may substitute for formal degrees.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.