Senior High-Speed IO Validation Engineer

Job Title

Senior High-Speed IO Validation Engineer

Role Summary

Join the hardware product validation team to own end-to-end validation of high-speed IO for next-generation GPU, CPU, and HPC platforms. The role focuses on system-level bring-up, validation planning, automation, and cross-functional debug from early silicon to production.

Experience Level

Senior-level. The role expects 3+ years of post-silicon HSIO validation or system bring-up experience.

Responsibilities

Primary responsibilities focus on validating and qualifying high-speed interfaces and delivering robust test coverage and debug for production releases.

• Define and execute HSIO validation plans: develop tests, metrics, resource plans, and automation.
• Validate high-speed interfaces across protocol, link, and physical layers (PCIe, NVLink, C2C, Ethernet, USB, DP, HDMI, CXL, SerDes, etc.).
• Bring up new hardware platforms and perform board- and system-level debug with design, firmware, and software teams.
• Review schematics, PCB layouts, and BOMs; provide development and component feedback for interoperability.
• Drive signal-integrity characterization, link tuning, margin analysis, and specification compliance.
• Define coverage from link bring-up through stress and corner-case scenarios, including error handling and power management.
• Develop and maintain test automation to scale validation and improve efficiency.
• Support manufacturing during NPI and mass production stages with engineering test and troubleshooting.

Requirements

Must-have technical skills, work requirements, and experience.

• 3+ years of post-silicon HSIO validation or system bring-up experience.
• Ability to work on site in a hardware lab 5 days a week at NVIDIA HQ (Santa Clara, CA).
• Solid understanding of at least one high-speed interface protocol and its PHY/link behavior (examples: PCIe, NVLink, C2C, Ethernet, USB, CXL, Display, SerDes).
• Hands-on experience with lab equipment such as high-bandwidth oscilloscopes, BERTs, protocol/logic analyzers, protocol exercisers, and TDR.
• Proven system-level debug skills on complex hardware platforms.
• Strong verbal and written communication and ability to collaborate across teams and suppliers.

Nice-to-have:

• Deep PCIe physical and link-layer debug experience including link training, equalization, and lane margining.
• Experience with NVLink, C2C, or other proprietary chip-to-chip interconnects.
• Strong signal integrity background: SerDes equalization, eye/margin analysis, jitter decomposition, and channel modeling.
• Experience validating high-speed Ethernet (multi-Gbps to 400G+/800G) or DisplayPort/HDMI.
• Experience with CXL protocols and memory-coherency validation over shared PCIe Gen5/6 PHYs.

Education Requirements

BS or higher in Electrical Engineering (EE), Computer Engineering (CE), or a related technical field is expected, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.