Senior FPGA Engineer

Job Title

Senior FPGA Engineer

Role Summary

Lead development of real-time FPGA processing infrastructure for a distributed sensing system. Migrate radar and signal‑processing pipelines from software to FPGA-based, low-latency, high-throughput implementations using SDR and RFSoC platforms.

Small, highly technical team; role spans prototype validation through productization and requires close collaboration with radar, DSP, RF, and software engineers.

Experience Level

Senior — typically 5+ years of FPGA engineering, real-time signal processing, or high-performance embedded systems experience.

Responsibilities

Primary responsibilities include design, implementation, testing, and optimization of FPGA-based real-time processing pipelines.

• Own FPGA development from prototype through productization.
• Define FPGA and real-time processing architecture; optimize throughput and latency.
• Lead hands-on bring-up, testing, debugging, and performance validation on real hardware.
• Develop and optimize fixed-point DSP pipelines for real-time workloads.
• Integrate FPGA pipelines with radar, DSP, software, and SDR systems.
• Conduct system-level trade studies across performance, latency, scalability, and implementation complexity.
• Support SDR platforms, RFSoC hardware, and real-world prototype testing.
• Drive transition from software-based prototypes to scalable FPGA deployments and define long-term FPGA strategy.

Requirements

Must-have technical skills, experience, and logistical constraints.

• Hands-on experience developing FPGA systems using VHDL, Verilog, or SystemVerilog in real hardware environments.
• Demonstrated ownership of complex FPGA or real-time systems from concept through validation or deployment.
• Strong understanding of signal-processing pipelines, system-level tradeoffs, and low-latency FPGA implementation.
• Experience with Python and C/C++ for integration, embedded development, testing, or tooling.
• Familiarity with DSP concepts such as FFTs, beamforming, channelization, synchronization, and filtering.
• Experience with modern FPGA architectures, including SoC FPGA or RFSoC platforms; experience with AMD/Xilinx tools (Vivado, Vitis, Vitis HLS).
• Familiarity with Git-based development workflows and modern software engineering practices.
• Ability to reason from first principles and make architectural tradeoffs; operate effectively in fast-paced, low-structure environments.
• Experience working in complex RF domains such as radar, SDR, or satellite communications.
• ITAR eligibility required: U.S. citizen, lawful permanent resident, protected individual as defined by ITAR, or able to obtain required authorizations.
• On-site presence required in San Francisco, CA.

Nice-to-have:

• Knowledge of radar system engineering or passive sensing architectures.
• Familiarity with AXI4/AXI-Stream, PCIe, JESD204B/C, Ethernet, and other high-speed interconnects.
• Experience with timing closure, floorplanning, hardware performance optimization, SDR systems, hardware-in-the-loop testing, PetaLinux, embedded Linux, or FPGA/software co-design.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent industry experience.

About the Company

Company: AdAstra

AdAstra Talent Advisors is a headhunting and talent-advising firm specializing in Climate, Space, and Defense hard-tech. They place technical and executive talent with early-stage and growth startups, focusing on long-term relationships and high-impact hires.