Senior DFT Engineer - LPU

Job Title

Senior DFT Engineer - LPU

Role Summary

Lead DFT implementation and silicon testability for high-performance SoC/GPU blocks. The role focuses on SCAN, MBIST, JTAG, ATPG, and related DFT structures and works across RTL-to-GDS flows, physical design, post-silicon bring-up, and CAD methodology teams.

Collaborate with post-silicon and STA teams to ensure DFT timing closure, enable robust test vector generation, and introduce CAD/DFT optimizations to improve test efficiency. Applications accepted until 2026-05-15.

Experience Level

Senior-level. Requires 5+ years of industry experience in DFT for high-performance ASICs/SoCs.

Responsibilities

Key responsibilities include building DFT structures, producing test patterns, and supporting silicon bring-up and test optimization.

• Define and implement SCAN, MBIST, JTAG, and debug structures for large SoC blocks.
• Drive creation of ATPG and MBIST test vectors and test pattern translation.
• Develop DFT timing constraints and coordinate with Physical Design and STA for timing closure in DFT mode.
• Work with post-silicon teams to bring up test patterns on silicon and debug failures on ATE.
• Collaborate with CAD/methodology teams to introduce AI-driven DFT/CAD optimizations.
• Support yield estimation, test optimization, and scan-compression strategies.

Requirements

Must-have technical skills and experience.

• 5+ years of hands-on DFT experience for large SoC/ASIC projects.
• Practical experience with SCAN, MBIST, and test generation tools and processes.
• Domain expertise in ATPG, scan compression, test pattern translation, yield learning, MBIST, LBIST, and IEEE 1500.
• Familiarity with ATPG Streaming Scan Network (SSN) implementation.
• Experience with UDFMs such as Cell Aware and Small Delay Defect analysis.
• Experience with RTL-to-GDS methodologies and formal equivalence checking.
• Strong scripting and coding skills in Tcl and Python.
• Proven experience debugging DFT test sequences on ATE and resolving silicon issues.
• Strong interpersonal and organizational skills; effective cross-team collaborator.

Nice-to-have:

• Experience applying AI-driven optimizations in CAD/DFT flows.
• Prior work on high-performance GPU or complex SoC designs.

Education Requirements

Bachelor's or M.S. in Computer Engineering or Electrical Engineering, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.