Senior DFT Engineer / Lead

Job Title

Senior DFT Engineer / Lead

Role Summary

Lead DFT architect for advanced multi-chip SoC programs targeting 7nm and below. The role drives DFT architecture, strategy, and delivery across tape-outs while coordinating with design, verification, and foundry teams.

Experience Level

Senior — typically 15+ years of experience in DFT and SoC design.

Responsibilities

Primary responsibilities include:

• Define and own DFT architecture for multi-chip SoC projects (7nm and below).
• Develop and execute scan, ATPG, MBIST, memory repair, OCC and LBIST strategies.
• Specify and implement BSD (ACJTAG/DCJTAG) schemes where required.
• Use Mentor and Synopsys DFT tool flows to achieve testability and coverage goals.
• Create and validate SDC constraints; run RTL and gate-level simulations for DFT validation.
• Address SerDes testability and DFT closure for high-speed interfaces.
• Develop automation and infrastructure using TCL/Perl/Python.
• Mentor engineers, lead cross-functional teams, and drive multiple tape-outs to production.

Requirements

Must-have technical skills and experience:

• Proven experience with scan, ATPG, MBIST, memory repair, OCC and LBIST.
• Experience with BSD (ACJTAG/DCJTAG) implementations.
• Proficiency with Mentor and Synopsys DFT toolsets and flows.
• Practical skills in SDC constraints, RTL and gate-level simulation.
• SerDes testability experience.
• Hardware description languages: Verilog/SystemVerilog.
• Scripting and automation: TCL, Perl, Python.
• Track record of multiple tape-outs in 7nm or below technologies.
• Leadership experience coordinating DFT teams and cross-discipline integration.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or a related technical field.

About the Company

Company: Sivaltech

Sivaltech provides semiconductor design and engineering services focused on DFT, SoC/IC design, verification, and IP development for advanced process nodes, supporting tape-outs, verification, and embedded software.