Senior ASIC/VLSI Engineer — SoC Tapeout Expert

Job Title

Senior ASIC/VLSI Engineer — SoC Tapeout Expert

Role Summary

Senior engineer role supporting pre-silicon SoC design and tapeout activities for advanced semiconductor and AI/networking programs with tier-1 clients. Position is permanent, full-time, and fully onsite in Silicon Valley.

Experience Level

Senior — requires 8+ years of pre-silicon ASIC/VLSI experience.

Responsibilities

The role focuses on RTL-driven SoC design and tapeout readiness across the ASIC lifecycle.

• Lead and execute RTL-based design tasks for SoC blocks and integrations.
• Drive tapeout readiness activities, including signoff coordination and issue resolution.
• Coordinate with verification, backend/physical-design, and system teams throughout the ASIC lifecycle.
• Analyze and resolve timing, integration, and design-for-manufacturing issues prior to tapeout.
• Work onsite with clients and program teams to meet schedule and quality targets.

Requirements

Core qualifications and relevant skills for immediate contribution.

• Must-have:
  • 8+ years of pre-silicon ASIC/VLSI engineering experience.
  • Strong RTL-based design background (design and integration experience).
  • Proven knowledge of the ASIC lifecycle and tapeout processes.
• Nice-to-have:
  • Experience with AI or networking SoC programs and tier-1 customer engagements.
  • Familiarity with EDA tools, physical design flows, timing closure and signoff.
  • Scripting skills for debug and automation (e.g., Python, TCL).

Education Requirements

Not specified.

About the Company

Company: CodeGeniusRecruit

Recruiting/staffing firm focused on technology and engineering roles, matching candidates with employers for remote, contract, and full-time positions.