Senior ASIC Design Verification Engineer

Job Title

Senior ASIC Design Verification Engineer

Role Summary

Senior engineer on the Circuit Solutions Group responsible for unit- and subsystem-level verification of custom IPs for GPUs and SoCs. The role drives verification sign-off strategies, verification infrastructure, and collaborates with design and partner teams to enable system integration.

Experience Level

Senior level. The role expects multiple years of hands-on verification experience; engineering candidates typically have 5+ years in unit/subsystem verification (see Education Requirements for degree-related guidance).

Responsibilities

Key responsibilities include ownership of verification for IPs, verification infrastructure, and cross-team integration.

• Develop and verify innovative IPs for hardware security, clocking, voltage regulation and silicon correlation.
• Own unit- and sub-system level verification: create functional test plans and execute verification using advanced tools and methodologies.
• Build, improve and maintain verification infrastructure and methodologies to meet custom IP requirements.
• Participate in design-specification discussions on architecture, intent, and implementation.
• Work with partner teams to enable system-level test development, debug, and delivery of verification IPs.
• Develop and deploy agentic AI frameworks to support DV workflows (stimulus generation, regression triage, debug, root-cause analysis).

Requirements

Technical skills and experience required or strongly preferred. Education details are listed under Education Requirements below.

Must-have

• Proficiency in Verilog, SystemVerilog, UVM, SVA and functional coverage development.
• Experience with VCS or equivalent simulators (e.g., Questa) and strong simulation/debug skills.
• Object-oriented programming experience and strong debugging and analytical ability.
• Experience developing verification plans and delivering verified RTL to sign-off.
• Continuous improvement mindset and focus on delivering correct first silicon.

Nice-to-have

• Experience developing agentic AI workflows using LLMs and industry agent frameworks for DV automation.
• Knowledge of custom IPs, behavioral real-number modeling, co-simulation (VCS-XA or equivalent), gate-level simulation, or formal equivalence.
• Scripting/automation skills (Perl, Tcl, Makefiles) and test automation experience.
• Strong interpersonal skills and experience working with distributed on-site and remote teams.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) or equivalent practical experience is stated as a baseline (typically with 5+ years verification experience). A Master’s degree in Electrical or Computer Engineering is preferred (typically with 3+ years verification experience). The posting allows equivalent experience in lieu of a degree.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.