Senior ASIC Design Engineer, Low Power Audio AI Subsystems

Job Title

Senior ASIC Design Engineer, Low Power Audio AI Subsystems

Role Summary

Lead design and implementation of ultra-low-power digital audio and AI IP blocks and subsystems within a low-power SoC. Work on micro-architecture, RTL implementation, power analysis, and integration with other IP and SoC teams.

Part of Qualcomm's audio ASIC team focused on low-power subsystems for mobile, compute, automotive, and IoT markets.

Experience Level

Senior. The listing specifies a minimum of 2+ years of professional industry ASIC hardware design and/or implementation experience.

Responsibilities

Primary technical responsibilities include architecture, RTL design, and power optimization across module, sub-system, and SoC levels.

• Develop micro-architecture and module specifications for digital audio and AI IP blocks and SoC interfaces.
• Implement modules and subsystems in synthesizable Verilog/VHDL RTL and integrate IP from other teams.
• Analyze performance, area, power, and cost trade-offs for different implementations.
• Identify and implement power-optimization opportunities for ultra-low-power designs; perform power projections and what-if scenario analysis.
• Collaborate with verification teams to debug module, subsystem, and SoC tests pre- and post-silicon.
• Work with implementation teams to review synthesis results, power metrics, and achieve static timing closure.
• Support silicon debug and correlate silicon results with functional and power objectives.

Requirements

Must-have technical skills and constraints below. Preferred skills are listed separately.

• 2+ years of professional industry ASIC hardware design and/or implementation experience.
• Proficient in writing clean, readable, synthesizable Verilog or VHDL RTL.
• Solid understanding of ASIC/VLSI concepts and design flow.
• Experience with logic synthesis using Synopsys and/or Cadence tools.
• Legal eligibility to work in Canada.

Nice-to-have / preferred:

• Experience with power analysis, power modeling, and low-power RTL design.
• Clock-domain crossing techniques and low-power design methodology.
• Experience with audio IP cores, DSP, audio interfaces (I2S, PCM, SLIMbus, SoundWire, Audio Codec) and low-power AI/ML accelerators.
• Familiarity with toolflows such as DC, IC Compiler/Place & Route, PrimeTime, Power Compiler, ModelSim/Modeltech, VCS, and power-theater tools.
• Experience with design rule checking (Spyglass), formal verification (Formality, LEC), and power simulation.
• Scripting skills (Python, Perl, TCL) and C programming.
• Knowledge of bus protocols (APB, AHB, AXI), post-silicon debug, and UVM.

Education Requirements

The posting specifies one of the following educational options: a Bachelor's degree in Science, Engineering, or a related field (with 2+ years ASIC design or verification experience); OR a Master's degree in Science, Engineering, or a related field (with 1+ years ASIC design or verification experience); OR a PhD in Science, Engineering, or a related field.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.