RTL Design Engineer, Sr Staff

Job Title

RTL Design Engineer, Sr Staff

Role Summary

Senior RTL engineer on the Connectivity Networking SoC team responsible for microarchitecture, RTL coding, and maintaining RTL quality for SOC/subsystem IP blocks. The role coordinates with verification, physical design, software and FPGA teams to meet area, power and performance targets through to tapeout.

Work focuses on high-performance SoC design for advanced process nodes targeting AI datacenter connectivity products.

Experience Level

Senior — typically 6+ years with a Bachelor's, 5+ years with a Master's, or 4+ years with a PhD (see Education Requirements for details).

Responsibilities

Key responsibilities include microarchitecture and RTL implementation, RTL quality assurance, and cross-team integration to deliver SoC/subsystem IP.

• Micro-architect and implement RTL for SoC subsystems and IP blocks.
• Develop UPF (power intent) and perform CLP checks.
• Perform RTL quality checks (lint, CDC, LEC) and address issues reported by verification.
• Create and maintain hardware block documentation and microarchitecture documents.
• Develop synthesis constraints and support synthesis flows for blocks and subsystems.
• Work with SOC architects and leads to integrate designs, review/ sign-off verification plans, DFT, and physical design implementation.
• Support verification, physical design, software and FPGA teams through debug, analysis, and fixes to ensure successful tapeout.

Requirements

Must-have technical skills and proven experience for successful execution in this role; nice-to-have items are listed separately.

• Must-have:
  • Multi-year, multi-project experience in RTL SoC design using Verilog/VHDL.
  • ASIC/FPGA debug methodologies and post-silicon bring-up experience.
  • Expertise with synthesis flows (Design Compiler) and formal verification (LEC).
  • Strong understanding of timing closure and static timing analysis.
  • Experience reviewing high-level test plans and coverage metrics.
  • Effective communication and teamwork skills; ability to coordinate across engineering functions.
• Nice-to-have:
  • Experience with SerDes PHY, DSP blocks, or analog mixed-signal integration.
  • Knowledge of Ethernet, PCIe standards, or other high-speed IO protocols.
  • Familiarity with bus protocols (AHB, AXI), memory controller designs, microprocessors, or chip IO/packaging.

Education Requirements

Qualification options in the posting: Bachelor's degree in Science, Engineering, or related field with 6+ years ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or related field with 5+ years experience; OR PhD in Science, Engineering, or related field with 4+ years experience. Fields referenced: science and engineering disciplines related to ASIC/SoC development.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.