Remote ASIC Verification Engineer (UVM/SystemVerilog)

Job Title

Remote ASIC Verification Engineer (UVM/SystemVerilog)

Role Summary

Contract ASIC verification role focused on UVM/SystemVerilog-based functional verification of ASIC/SoC designs. The position is a 6-month engagement and can be performed 100% remotely.

The engineer will produce and execute verification plans, develop UVM testbenches, run regressions, and collaborate with design engineers to close functional bugs and coverage gaps.

Experience Level

Mid-level / Mid-Career. Specific years of experience not specified.

Responsibilities

Primary responsibilities include planning and implementing verification strategies and delivering runnable verification environments and results.

• Develop and maintain UVM/SystemVerilog testbenches and verification infrastructure.
• Create verification plans, test cases, and constrained-random tests.
• Run regression suites, analyze failures, and debug issues with RTL and testbench.
• Measure functional coverage and drive coverage closure activities.
• Document verification results and communicate findings to the design team.

Requirements

Must-have technical skills and expectations for the role.

• Proven experience in ASIC/SoC functional verification.
• Proficiency with UVM and SystemVerilog for testbench development.
• Experience with simulation and regression-based verification workflows.
• Able to work independently in a fully remote, contract engagement and available to start as soon as possible.
• Good debugging and problem-solving skills; ability to collaborate with RTL designers.

Education Requirements

Not specified.

About the Company

Company: CodeGeniusRecruit

Recruiting/staffing firm focused on technology and engineering roles, matching candidates with employers for remote, contract, and full-time positions.