Remote ASIC Verification Engineer (UVM/SystemVerilog)

Job Title

Remote ASIC Verification Engineer (UVM/SystemVerilog)

Role Summary

Contract ASIC Verification Engineer responsible for functional verification of ASIC/SoC designs using UVM and SystemVerilog. This is a 6-month, full-time contract performed 100% remotely as an individual contributor role.

Experience Level

Mid-level. Specific years of experience were not stated.

Responsibilities

Key responsibilities include:

• Design and implement UVM/SystemVerilog verification environments and testbenches.
• Create and execute verification plans and test cases to validate ASIC/SoC functionality.
• Develop functional coverage models and track coverage metrics.
• Run simulations, analyze failures, and debug RTL/verification issues.
• Collaborate with RTL designers and system engineers to resolve defects.
• Document verification results and maintain test infrastructure.

Requirements

Must-have qualifications:

• Strong background in functional verification.
• Proficiency with UVM and SystemVerilog-based verification methodologies.
• Knowledge of ASIC/SoC design and verification concepts.
• Ability to work independently in a remote setting and meet contract timelines.
• Available to start as soon as possible for a 6-month contract.

Education Requirements

Not specified.

About the Company

Company: CodeGeniusRecruit

Recruiting/staffing firm focused on technology and engineering roles, matching candidates with employers for remote, contract, and full-time positions.