R&D Engineering Senior Architect

Job Title

R&D Engineering Senior Architect

Role Summary

Lead architecture and development of placement and routing infrastructure for Synopsys Custom Compiler focused on advanced process nodes (5nm, 3nm, 2nm, 14A). Work with IP and custom design teams to produce layout automation features that improve designer productivity and reduce time-to-tapeout.

The role combines hands-on development, setting technical direction, and mentoring engineers within the Custom Compiler engineering organization.

Experience Level

Senior — requires extensive EDA engineering and architecture experience. The posting specifies 15+ years of related experience with a Bachelor's degree or 13+ years with an advanced degree; equivalent practical experience is considered.

Responsibilities

Primary duties include designing and delivering placement and routing automation and leading architectural direction for Custom Compiler.

• Architect and implement placement and routing infrastructure for advanced GAA and FinFET nodes.
• Design layout automation features to improve circuit layout productivity for custom and analog designs.
• Set technical direction and operational specifications based on customer workflows and EDA ecosystem requirements.
• Drive R&D of new algorithms and tools to remove bottlenecks in custom IC layout.
• Collaborate with semiconductor IP teams to integrate layout automation into internal flows.
• Mentor and guide junior engineers on software architecture, coding standards, and quality practices.
• Manage maintenance and evolution of existing tools across product releases, balancing stability and new features.

Requirements

Must-have technical skills and experience relevant to building production EDA software for custom IC layout.

• Hands-on development experience with Custom Compiler or Cadence Virtuoso (development or power-user level).
• Deep expertise in placement and routing algorithms for analog, mixed-signal, or custom digital layouts.
• Proven ability to architect software systems that balance performance, maintainability, and extensibility in complex EDA environments.
• Direct experience with advanced process nodes (7nm or below) and their layout constraints.
• Experience collaborating with semiconductor IP or custom IC design teams.
• Strong coding practices: writing maintainable code, setting coding standards, and ensuring quality.
• Effective communicator able to present technical direction to leadership and cross-functional teams.

Education Requirements

The posting specifies either a Bachelor’s degree with a minimum of 15 years of related experience, or an advanced degree with a minimum of 13 years of related experience. Preferred fields include Computer Science or Electrical Engineering; equivalent practical experience is acceptable.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.