Principal SoC Design Engineer, HBM

Job Title

Principal SoC Design Engineer, HBM

Role Summary

Hands-on SoC design engineer in the Heterogeneous Integration Group responsible for RTL design, IP integration, and pre-/post-silicon support for HBM logic die. Works cross-functionally with architecture, verification, physical design, firmware, and product teams to deliver high-performance, manufacturable SoC solutions.

Experience Level

Senior — preferred minimum 10 years of relevant experience (as stated in the posting).

Responsibilities

Primary responsibilities focus on RTL development, IP integration, system-level integration, and silicon bring-up support.

• Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die.
• Integrate internal and third-party IP (controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY-adjacent logic).
• Translate architectural and micro-architectural specifications into RTL in collaboration with SoC architects.
• Participate in SoC-level integration: clocking, resets, power intent, and configuration infrastructure.
• Support verification and debug of simulation, emulation, and formal results; resolve functional, performance, and connectivity issues.
• Collaborate with physical design on synthesis, timing, power, and floorplanning considerations.
• Assist with pre-silicon validation and post-silicon bring-up including root-cause analysis of silicon issues.
• Produce and maintain design documentation, block specifications, and design reviews; improve design quality and reuse through best practices and automation.

Requirements

Must-have technical skills and proven experience for successful performance in this role.

Must-have:

• Strong experience in digital SoC design and RTL development.
• Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
• Experience with RTL-to-GDS flow, including synthesis, static timing analysis, and design sign-off considerations.
• Working knowledge of design verification concepts and debug workflows.
• Experience integrating complex IP blocks into large SoCs and familiarity with EDA tools (Cadence, Synopsys, Siemens).
• Programming or scripting experience (Python, TCL, Perl, or shell scripting).
• Strong analytical and problem-solving skills and ability to work effectively in a global, cross-functional engineering environment.

Nice-to-have:

• Experience with HBM, DRAM, or memory-centric SoC designs.
• Familiarity with high-speed interfaces, clocking strategies, reset architectures, and power management concepts.
• Exposure to DFT concepts (scan, MBIST, BIRA/BISR) and debug.
• Experience with hardware emulation or acceleration platforms (Palladium, Veloce, Zebu).
• Proven ability to mentor and develop junior engineers.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. The posting also states a preferred minimum of 10 years of experience in a related field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.