Principal SoC Design Engineer

Job Title

Principal SoC Design Engineer

Role Summary

This individual contributor leads end-to-end SoC design for high-performance data processing units and automotive microcontrollers, from architecture and micro-architecture to RTL implementation and silicon-proven delivery.

Works within the SoC design team and collaborates with architecture, verification, physical design, DFT, and software teams to meet performance, power, and area targets for advanced-node, safety-critical products.

Experience Level

Senior — 8-10+ years of hands-on SoC/IP design experience.

Responsibilities

Primary responsibilities include:

• Translate subsystem and SoC-level requirements into micro-architecture specifications that meet performance, power, and area targets.
• Architect and implement synthesizable RTL (SystemVerilog/Verilog) for IP modules, subsystems, and full SoC integrations.
• Drive front-end design flow improvements, automation, and IP reuse strategies to increase productivity and quality.
• Perform RTL design reviews and optimize for timing, power, and area; develop constraints to support first-pass silicon success.
• Evaluate and integrate standards, interconnects, and processor architectures (e.g., AXI/CHI, AMBA, RISC-V, ARM) into production flows.
• Collaborate with cross-functional teams to resolve multi-disciplinary issues and define system-level tradeoffs.
• Provide technical guidance via code reviews, mentoring, and documentation of best practices for maintainable, verifiable RTL.
• Analyze silicon bring-up results, debug field issues, and implement design and methodology improvements based on lessons learned.

Requirements

Must-have skills and experience:

• 8-10+ years of hands-on SoC/IP design experience, including architecture-to-silicon delivery for high-volume or safety-critical applications.
• Expert-level proficiency in synthesizable SystemVerilog/Verilog and advanced digital design techniques (pipelining, FSM optimization, low-power design).
• Deep knowledge of SoC interconnects and protocols such as AXI4/5, AHB, APB, CHI, and NoC fabrics.
• Proven experience leading RTL development for complex blocks (processors, accelerators, peripherals) on advanced nodes (7nm and below).
• Proficiency in scripting for RTL generation and automation (Python, Tcl, Perl).
• Strong analytical, debugging, and problem-solving skills for resolving ambiguous cross-domain issues.
• Excellent technical communication skills for presenting designs and documenting specifications.
• Demonstrated ability to collaborate across architecture, verification, physical design, DFT, and software teams.

Nice-to-have:

• Experience with RISC-V, ARM Cortex-A/R/M, or MIPS in automotive/embedded applications.
• Functional Safety (ISO 26262 ASIL-D) experience, including safety mechanisms and certification flows.
• Familiarity with register description languages (IP-XACT, SystemRDL) and UVM-based verification methodologies.
• Experience with DSPs, AI accelerators, or vision pipelines and with synthesis/EDA tools adoption (e.g., Synopsys).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering as stated in the posting.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.