Principal RFIC Design Engineer

Job Title

Principal RFIC Design Engineer

Role Summary

Join the core RFIC design team to design, simulate, and validate mmWave front-end blocks (LNAs, PAs, phase shifters, VGAs, mixers) and full transceiver chains for next-generation beamformer ASICs. This senior, hands-on role includes architecture input, ownership from schematic to silicon, and close collaboration with founding engineers at an early-stage fabless semiconductor company.

Experience Level

Senior — advanced experience required. Typical background: MS + 5 years industry experience or PhD + 2 years industry experience in RF/mmWave IC design.

Responsibilities

Primary responsibilities include design, simulation, validation, and support through silicon bring-up.

• Design mmWave front-end circuit blocks (PAs, LNAs, phase shifters, VGAs, mixers) in advanced CMOS or RFSOI.
• Perform transistor-level schematic design, simulation, and optimization using Cadence Virtuoso (Spectre, ADE).
• Lead or coordinate full-custom layout and ensure DRC/LVS-clean designs at mmWave frequencies.
• Perform post-layout extraction and EM simulation (Ansys HFSS, EMX, ADS Momentum) to validate parasitic effects.
• Support tapeout preparation, design reviews, and documentation.
• Lead silicon bring-up, bench characterization, and debugging of fabricated chips.
• Collaborate on chip-level architecture and system partitioning for multi-channel beamformer ICs.
• Mentor junior RFIC designers and promote technical best practices.

Requirements

Must-have technical skills and proven experience:

• Demonstrated expertise in at least two of: PA, LNA, phase shifter, VGA, mixer, or frequency multiplier design at mmWave frequencies.
• Expert proficiency with Cadence EDA suite (Virtuoso, ADE, Layout) and EM simulation tools (Ansys HFSS, EMX, or ADS Momentum).
• Experience with at least one complete tapeout cycle: schematic → layout → fabrication → bring-up → characterization.
• Strong understanding of mmWave transmission-line theory, matching networks, and on-chip passive design.
• Experience performing post-layout extraction and EM validation to account for parasitics.
• Track record of published work or shipped products demonstrating circuit design excellence.
• Ability to work in a small-team/startup environment and communicate design tradeoffs clearly.

Nice-to-have:

• Phased-array or multi-channel beamformer IC design experience.
• Background in SATCOM, 5G NR FR2, or automotive radar mmWave applications.
• Experience in SOI nodes with high-resistivity substrates.
• Familiarity with system-level RF specs: EVM, P1dB, noise figure, IP3, EIRP, G/T.

Education Requirements

MS in Electrical Engineering with 5+ years industry experience, or PhD in Electrical Engineering with 2+ years industry experience, focused on RF/mmWave IC design.

About the Company

Company: Oso Semiconductor

Headquarters: Mountain View, CA, United States

Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.