Principal Engineer – Physical Design

Job Title

Principal Engineer – Physical Design

Role Summary

The Principal Engineer will lead full-chip APR/physical implementation (netlist-to-GDSII) activities for advanced mixed-signal and digital designs. You will work on hierarchical, low-power, multi-mode, multi-corner designs as part of a distributed CAD Physical Design team supporting multiple product groups.

This role emphasizes technical ownership of physical implementation flows, timing closure, sign-off readiness, and cross-team coordination to deliver manufacturable silicon on schedule.

Experience Level

Senior — requires substantial experience; the posting specifies 10+ years of relevant physical design experience.

Responsibilities

Primary responsibilities include ownership of full-chip physical implementation and delivery of sign-off quality layouts.

• Lead and execute full-chip APR/physical implementation (netlist-to-GDSII) for large hierarchical designs.
• Develop and optimize floorplanning, placement, clock tree synthesis, routing, and timing-closure strategies.
• Manage sign-off flows including STA, formal equivalence, parasitic extraction, power integrity, and physical verification.
• Implement and verify UPF-based low-power strategies across the physical design flow.
• Collaborate with RTL, verification, DFT, and layout teams to resolve physical and timing issues.
• Automate and script flows to improve repeatability and throughput; mentor junior engineers and share best practices.
• Support technology-porting activities and ensure manufacturability for target process nodes.

Requirements

Must-have technical skills and professional attributes.

• Hands-on experience in physical-design flows: floorplanning, placement optimization, CTS, routing, crosstalk avoidance, and physical verification.
• Advanced knowledge of place-and-route methodologies, VLSI logic principles, clock architectures, and techniques for timing closure.
• Deep experience with sign-off tool flows for STA, formal equivalence checking, parasitic extraction, power integrity, and physical verification.
• Practical experience with UPF and low-power implementation across the full physical flow.
• Daily usage of ICC/ICC2 or Cadence Innovus preferred.
• Experience with 40nm or 28nm technologies required; 16nm or smaller preferred.
• Proficiency in Tcl and Perl scripting for flow automation and debugging.
• Strong written and verbal communication, problem-solving skills, and ability to coordinate across geographically distributed teams.
• Travel: up to 25% as needed. Typical on-site/office work expected.

Education Requirements

Bachelor's or Master’s degree in Electrical or Electronics Engineering. The posting specifies 10+ years of relevant experience; degree requirement is explicit in the source.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.