Principal Engineer – Physical Design

Job Title

Principal Engineer – Physical Design

Role Summary

Lead full-chip physical implementation (Netlist-to-GDSII) and sign-off activities for complex hierarchical, low-power, multi-mode, multi-corner mixed-signal ASICs. Work on physical implementation tasks including floorplanning, placement, clock tree synthesis, routing and physical verification as part of a global CAD/Physical Design team.

This role focuses on driving timing closure, sign-off readiness, and manufacturable implementation while collaborating with RTL, verification, and layout teams.

Experience Level

Senior — requires significant hands-on experience; the posting calls for 10+ years of relevant physical design experience.

Responsibilities

Primary responsibilities include leading and executing full-chip physical design and sign-off activities.

• Lead APR/physical implementation from netlist to GDSII for full-chip designs.
• Perform floorplanning, placement optimization, clock tree synthesis, routing, and crosstalk avoidance.
• Drive timing closure and collaborate on clock structures and VLSI timing issues.
• Coordinate sign-off flows: static timing analysis, parasitic extraction, power integrity, formal equivalence, and physical verification.
• Implement low-power flows and UPF-aware physical strategies across the design flow.
• Collaborate with cross-functional and geographically distributed teams to meet design goals and schedules.
• Provide technical leadership and mentorship to other designers.

Requirements

Key must-have skills and technologies for successful performance in this role.

• Must-have: 10+ years of relevant physical design experience.
• Must-have: Hands-on experience with floorplanning, placement, CTS, routing, and physical verification.
• Must-have: Advanced knowledge of place-and-route methodologies, VLSI logic principles, and timing closure techniques.
• Must-have: Experience with sign-off tools and flows for STA, parasitic extraction, power integrity, formal equivalence, and physical verification.
• Must-have: Experience with 40nm or 28nm process technologies.
• Must-have: Proficiency in Tcl and Perl scripting; strong debugging and problem-solving skills.
• Must-have: Excellent written and verbal communication and ability to work across distributed teams.
• Nice-to-have: Daily use of ICC/ICC2 or Innovus.
• Nice-to-have: Experience with 16nm or smaller technologies.
• Nice-to-have: Willingness to travel up to ~25% as needed.

Education Requirements

Bachelor's or Master's degree in Electrical or Electronics Engineering.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.