Principal Engineer - IP Design Verification

Job Title

Principal Engineer - IP Design Verification

Role Summary

Senior verification engineer responsible for IP and subsystem verification for SoC products. Lead verification strategy, architect scalable UVM testbenches, and drive metric-driven coverage closure using automation and AI/ML techniques.

Work closely with Architecture, RTL, emulation, SoC verification and validation teams to deliver high-quality, reusable IPs for next-generation microcontrollers and microprocessors.

Experience Level

Senior — approximately 15 years of experience in IP/SoC verification.

Responsibilities

Lead verification activities across IP and subsystem scope, from specification to sign-off. Key responsibilities include:

• Define and drive IP-level verification strategies, test plans, coverage models, and closure criteria.
• Design and implement scalable, reusable UVM-based verification environments for IP and subsystem verification.
• Lead functional, code, assertion, and cross-coverage closure with clear metrics for sign-off.
• Apply AI/ML-assisted techniques to accelerate coverage convergence, identify stimulus gaps, and improve regression efficiency.
• Develop and execute constraint-random and directed tests for protocol, corner-case, and stress verification.
• Collaborate with RTL, architecture, emulation, and SoC verification teams to ensure correct IP integration.
• Translate specifications into verification plans, advanced checkers, scoreboards, assertions (SVA), and protocol monitors.
• Evaluate and adopt next-generation verification, coverage, and analytics tools with EDA vendors.
• Mentor junior engineers and promote verification best practices and continuous improvement.
• Support gate-level simulation, low-power verification, and post-silicon debug when required; ensure deliverables meet quality, schedule, and reusability targets.

Requirements

Must-have skills and experience:

• ~15 years experience in IP/SoC verification with industry-standard EDA tool experience.
• Strong expertise in UVM-based testbench architecture and development.
• Proven experience with metric-driven verification and functional/code coverage closure.
• Deep knowledge of SystemVerilog, UVM, and assertions (SVA); proficiency in Verilog/SystemVerilog.
• Experience with directed and constrained-random verification methodologies and debugging in simulation and emulation.
• Proficiency with C/C++ and shell scripting for test infrastructure and automation.
• Strong analytical, problem-solving, and communication skills.

Nice-to-have:

• Hands-on experience with AI/ML-based verification tools for coverage gap analysis, stimulus optimization, and regression triage.
• Scripting expertise in Python, Perl, or Tcl for automation and analytics.
• Exposure to formal verification and hybrid formal-simulation flows.
• Familiarity with high-speed or complex IPs (for example H.264, security, debug, or safety-critical IPs).

Education Requirements

Bachelor's or Master's degree in Electronics Engineering.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.