Principal Engineer, ASIC Design Verification

Job Title

Principal Engineer, ASIC Design Verification

Role Summary

Lead the verification strategy for a next-generation silicon photonic chip. Act as the technical lead to architect scalable UVM/SystemVerilog verification environments, define methodology, enable tape-out quality, and mentor a team of verification engineers.

Collaborate with architects and RTL designers on system-level and block-level verification, improve automation, and resolve complex hardware/firmware/verification issues.

Experience Level

Senior — Principal level. The posting specifies 12+ years of relevant ASIC/SoC verification experience.

Responsibilities

Primary responsibilities focus on verification architecture, methodology, debug, and team technical leadership.

• Architect modular, reusable, and scalable UVM/SystemVerilog testbenches for complex IP blocks and subsystems.
• Define and enforce verification methodology, coding standards, and coverage metrics; evaluate new EDA tools and flows.
• Collaborate early with architects and RTL designers to create verification plans and ensure micro-architecture testability.
• Lead root-cause analysis and debug of difficult hardware issues across RTL, firmware, and verification environments.
• Mentor engineers, perform design and code reviews, and promote engineering best practices.
• Develop automation and infrastructure for regression testing, performance analysis, and coverage closure.

Requirements

Must-have technical skills and experience; preferred skills noted as nice-to-have.

• Must-have: Expert-level SystemVerilog and UVM; proven experience building verification environments (agents, scoreboards, sequencers).
• Must-have: Deep knowledge of interface protocols such as PCIe, AMBA/AXI, UCIe, and ARM-related interfaces.
• Must-have: Strong proficiency in scripting for automation (Python, Perl, Tcl, or Shell).
• Must-have: Experience defining functional coverage and driving coverage closure.
• Must-have: Strong system-level debugging and problem isolation skills across RTL, firmware, and verification tools.
• Nice-to-have: Formal verification experience and writing SystemVerilog Assertions (SVA); experience with VC Formal or similar tools.
• Nice-to-have: Hands-on experience with hardware emulation/acceleration platforms.
• Nice-to-have: Familiarity with RISC-V or ARM processors, coherency protocols, mixed-signal verification, SerDes (PCS/PMA) verification, and HBM interfaces.
• Nice-to-have: C/C++ or SystemC modeling experience and formal model equivalence checking expertise.

Education Requirements

MS in Electrical Engineering, Computer Engineering, or a related field is specified in the posting. The role also specifies 12+ years of relevant ASIC/SoC verification experience.

About the Company

Company: Ayar Labs

Developer of co-packaged optics (CPO) that use light to move data at high speed with lower energy, targeting AI-scale interconnects. Their silicon photonics solutions aim to enable next-generation AI architectures and are backed by industry partners including NVIDIA, AMD, and Intel.