Principal DV Engineer - Interconnect (Silent)
Join the Neoverse interconnect verification team responsible for the coherent mesh network used in servers, networking, storage and AI systems. The role focuses on architecting and implementing verification strategies and SystemVerilog/UVM testbenches to validate complex interconnect, cache-coherent and memory subsystem features.
Senior β typically 7+ years of hands-on verification or RTL design experience is expected.
Primary duties include planning and executing verification for interconnect IP and driving methodology improvements.
Must-have technical skills and experience.
Nice-to-have:
Bachelor's, Master's, or PhD in Electrical/Computer Engineering or Computer Science (or equivalent technical degree).
Company: Arm
Headquarters: Cambridge, United Kingdom
ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.
