Principal Digital Design Engineer

Job Title

Principal Digital Design Engineer

Role Summary

Lead RTL design and delivery of complex IPs and subsystems for MCU SoCs, driving micro-architecture, ensuring PPA targets, and supporting SoC integration. The role includes technical leadership, cross-functional collaboration with verification, physical design, software and system architects, and mentoring junior engineers.

This position reports to the manufacturing/product engineering organization in Bengaluru and focuses on high-quality silicon delivery for MCU platforms.

Experience Level

Senior — requires extensive hands-on experience. The posting specifies a minimum of 15 years of digital IC/ASIC design experience.

Responsibilities

Deliver RTL and subsystem designs and ensure integration and quality across SoC projects.

• Lead RTL design and development of complex IPs and subsystems, meeting performance, power, and area (PPA) goals.
• Define micro-architecture and high-level digital design for assigned blocks.
• Support SoC integration by delivering subsystem views and documentation to back-end and verification teams.
• Own RTL quality checks (lint, CDC, RDC) and support functional verification efforts for assigned blocks.
• Collaborate with system architects, verification, physical design, and software teams to define specifications and ensure end-to-end integration.
• Mentor and provide technical guidance to junior engineers to raise team capability.
• Improve RTL design methodologies, coding guidelines, and design processes.

Requirements

Essential technical skills and experience required to perform the role.

• Minimum of 15 years of hands-on digital IC/ASIC design experience with delivered silicon.
• Strong RTL design experience using Verilog or VHDL.
• Solid understanding of digital design principles, timing analysis, clocking and resets, and verification methodologies.
• Experience with industry-standard EDA tools for synthesis, simulation, and static timing analysis.
• Proven problem-solving skills and ability to own blocks end-to-end.
• Ability to produce clear documentation and subsystem views for cross-functional teams.

Preferred:

• Experience owning complex IPs or subsystems in large SoCs and SoC-level integration.
• Background in micro-architecture and high-level digital design.
• Hands-on experience with RTL quality tools such as Spyglass (Lint, CDC, RDC).
• Experience with low-power design techniques and synthesis flows.
• Scripting experience in Shell, Perl, or Python; familiarity with applying AI to design workflows is a plus.

Education Requirements

Bachelor's degree in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, or a related technical field is specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.