Principal AMS Layout Engineer

Job Title

Principal AMS Layout Engineer

Role Summary

Lead and execute full‑custom analog and mixed‑signal layout for high‑speed SerDes IP across advanced process nodes. Own layout scope, schedules, deliverables, and quality signoff while collaborating with circuit designers, CAD, verification, and customer teams.

Develop and scale layout methodologies and workflows, perform hands‑on debugging, and mentor engineers to improve consistency, efficiency, and first‑time‑right results across global product lines.

Experience Level

Senior-level (Principal). Years of experience not specified in the posting.

Responsibilities

The role combines hands‑on layout work, methodology development, customer interfacing, and team mentorship.

• Define and manage layout scope, effort, schedules, deliverables, and customer requirements.
• Accelerate layout development for high‑speed SerDes IP to meet quality, schedule, and budget targets.
• Serve as the primary technical interface to customers and internal stakeholders; report status, risks, and mitigation plans.
• Gather customer requirements and translate them into technical specifications and workflow improvements.
• Perform hands‑on debugging and root‑cause analysis of complex layout issues.
• Collaborate on layout approaches that consider advanced packaging (2.5D/3D, interposers, bump strategy) where applicable.
• Develop, validate, and refine end‑to‑end layout workflows to improve quality and consistency.
• Innovate analog/mixed‑signal layout methodologies and integrate automation where appropriate.
• Ensure signoff quality across DRC/LVS, EM/IR, reliability, parasitics, and tapeout readiness.
• Create and maintain technical documentation, workflow guides, and customer deliverables.
• Mentor and coach junior engineers; promote best practices and cross‑team knowledge sharing.

Requirements

Key technical skills and tools required or strongly preferred.

• Must-have: In‑depth experience with high‑speed SerDes layout and analog/mixed‑signal circuits.
• Must-have: Strong hands‑on debugging, problem isolation, and root‑cause layout analysis skills.
• Must-have: Proficiency in custom layout tools (Synopsys Custom Compiler or equivalent).
• Must-have: Familiarity with verification tools such as ICV, Star‑RCXT, PERC, or equivalents.
• Must-have: Experience with high‑speed/signal‑integrity layout practices (differential routing, shielding, clock/data optimization).
• Must-have: Knowledge of reliability‑driven and parasitic‑aware layout practices (EM, IR, matching, symmetry).
• Must-have: Experience with project tracking tools (Jira/Atlassian or similar).
• Nice-to-have: Experience with multi‑Gbps NRZ and PAM4 SerDes.
• Nice-to-have: Experience with advanced packaging considerations (2.5D/3D, interposers, bump strategy).
• Nice-to-have: Porting‑friendly layout practices across nodes and foundries.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.