Physical Design Engineer (All Experience Levels)

Job Title

Physical Design Engineer (All Experience Levels)

Role Summary

As a Design Team member at Tylsemi, you will implement digital blocks and/or full-chip designs from netlist to tapeout. You will partner with RTL, verification, DFT, STA, and signoff teams to meet timing, power, testability, and manufacturability goals.

Experience Level

Open to all experience levels (0–30 years). Scope and ownership will vary by candidate seniority.

Responsibilities

Primary responsibilities span physical implementation, closure, and tapeout readiness.

• Own floorplanning, power planning, placement, CTS, routing, and ECO closure for blocks/subsystems or top-level designs.
• Develop and refine SDC constraints with RTL/STA; ensure constraints are complete and implementation-ready.
• Drive timing closure across modes and corners, including setup/hold closure, clock quality, and path optimization.
• Close physical signoff requirements: DRC/LVS, IR drop/EM, antenna, density/fill, and manufacturability checks.
• Analyze and resolve congestion, utilization, and routing challenges; propose floorplan or architectural improvements.
• Partner with STA and signoff teams to debug violations and implement clean, reviewable ECOs.
• Collaborate with DFT on scan/MBIST/DFT constraints and physical requirements to support testability goals.
• Support low-power implementation (UPF/CPF intent awareness), multi-voltage domains, level shifters/isolation, and power gating.
• Create and maintain flow automation, checks, and reporting (Tcl/Python) to improve predictability and execution speed.
• Contribute to tapeout readiness: documentation, checklists, design reviews, and root-cause analysis to prevent recurrence.

Requirements

Must-have skills and experience; scope will depend on seniority.

• Hands-on ASIC physical design implementation and closure experience.
• Strong understanding of digital design fundamentals, timing concepts, and physical effects (RC, crosstalk, clocking, variability).
• Systematic debug skills using reports and logs, with clear problem statements and action plans.
• Ability to work cross-functionally with RTL, verification, DFT, STA, and signoff teams to resolve issues.
• Good engineering hygiene: version control, reproducible runs, clean documentation, and review-friendly ECO practices.
• Must-have: ASIC design experience.
• Nice-to-have: Experience with P&R and signoff tools (Innovus/ICC2, PrimeTime, Calibre/ICV, RedHawk/Voltus or equivalents), advanced timing closure techniques (useful skew, CRPR, OCV/AOCV/POCV, SI-aware optimization), hierarchical design and multi-die/advanced packaging awareness, UPF/MCMM flows and power integrity closure, strong Tcl/Python scripting for PD automation, and foundry signoff/tapeout checklist experience.

Education Requirements

Not specified.

About the Company

Company: Tylsemi

Tylsemi builds and scales semiconductor operations, partnering across design, manufacturing, and supply chain to take silicon from concept to high-volume production with emphasis on speed, quality, and predictable execution.