Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Lead top-level signoff activities for complex SoCs on advanced process nodes (5nm / 3nm / 2nm). Collaborate with RTL, timing, power integrity, physical design, and foundry teams to ensure timing convergence, power reliability, and tapeout readiness for high-performance silicon.

Experience Level

Senior-level; typically requires 8+ years of experience in physical design or signoff and multiple advanced-node tapeouts.

Responsibilities

Deliver signoff closure and drive top-level signoff activities across timing, power, and clock domains. Key responsibilities include:

• Lead signoff-to-tapeout closure for full-chip SoC designs on advanced nodes (5nm / 3nm / 2nm).
• Collaborate with RTL, STA, power integrity, physical design, and foundry teams to resolve structural, timing, and power issues.
• Execute, analyze, and debug full-chip timing, power, reliability, and clocking problems.
• Develop and optimize signoff methodologies to improve turn-around time (TAT) and PPA.
• Identify and mitigate timing, power, reliability, and clocking risks; implement ECOs to meet closure.
• Perform top-level EM/IR analysis, full-chip STA, or clock-distribution design depending on assigned track.
• Deliver independent signoff closure and tapeout readiness.

Requirements

Must-have technical skills and experience:

• 8+ years in physical design/signoff with multiple full-cycle tapeouts (2–3 successful tapeouts on advanced nodes preferred).
• Deep knowledge of OCV, AOCV/POCV, and statistical timing methodologies.
• Strong scripting skills: Tcl, Python, Perl.
• Experience with signoff and PD tools such as Synopsys PrimeTime, Cadence Tempus, Cadence Innovus, Synopsys Fusion, Ansys RedHawk-SC, Cadence Voltus, and SPICE as applicable.
• Expertise in at least one specialized track: top-level EM/IR (power integrity), full-chip STA (timing), or clock-distribution/CTS.
• Familiarity with foundry signoff methodologies (TSMC, Samsung, Intel) and advanced-node constraints.
• Excellent debugging, analytical, and communication skills.
• Preferred: experience with 2.5D/3D IC packaging signoff, and background in HPC, AI accelerators, or large-scale SoC designs.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (as specified in the source posting).

About the Company

Company: Oso Semiconductor

Headquarters: Mountain View, CA, United States

Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.