Lead RTL Design Engineer

Job Title

Lead RTL Design Engineer

Role Summary

Lead RTL design and microarchitecture for a power-efficient processor/accelerator SoC. Own microarchitecture definition and RTL implementation across dataflow execution fabric, memory subsystem, on-chip interconnect/NoC, low-power logic, and peripheral IP integration from architecture spec through synthesis-ready RTL.

This role partners with architects, verification, physical design, firmware, and compiler teams and will influence product and process development as the hardware organization moves from early product development toward tape-out and volume production.

Experience Level

Senior — requires extensive RTL and SoC tape-out experience. The posting requests 8+ years of RTL design experience.

Responsibilities

Primary responsibilities include owning uArch and RTL delivery for assigned blocks, ensuring PPA targets, and coordinating cross-functional integration and bring-up.

• Define processor and compute-unit microarchitecture: dataflow pipelines, execution units, interfaces, and PPA targets.
• Design on-chip interconnects and drive system integration with physical design for performance and scalability.
• Define memory-subsystem interfaces, data movement, ordering, and synchronization models.
• Architect configuration, scheduling, and execution models for multi-kernel workloads and host interaction.
• Drive power architecture: clocking, resets, power domains, UPF-driven flows, and low-power strategies.
• Collaborate with compiler/software teams to co-design the hardware execution model and ensure efficient workload mapping.
• Author and own uArch specification documents and lead design reviews with stakeholders.
• Mentor RTL engineers, enforce coding standards, and perform RTL reviews focused on microarchitecture risk.
• Participate in PPA analysis loops: synthesize blocks, review area/timing/power, and make data-driven tradeoffs.
• Collaborate with DV leads on verification plans and provide directed tests for corner cases and power state transitions.
• Support silicon bring-up: DFT/scan guidance and RTL-level debug during lab validation.

Requirements

Must-have technical skills and experience required for the role.

• 8+ years of RTL design experience with tape-out ownership of dataflow-based designs, NoC/on-chip networks, memory subsystems, or peripheral integration on processor/accelerator SoCs.
• Deep proficiency in SystemVerilog for synthesis-clean, lint-clean, and timing-aware RTL; design of complex state machines, arbiters, token flow controllers, and datapaths.
• Solid understanding of parallel execution models (dataflow, SIMD, systolic arrays) and token-based producer-consumer synchronization.
• Hands-on experience with on-chip memory design: SRAM wrappers, scratchpad/TCM, banking, and memory-mapped register interfaces.
• Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, retention registers, and AON wakeup logic.
• Familiarity with at least one on-chip bus protocol at the RTL level (AXI, AHB, APB, TileLink, or NoC equivalent).
• Experience taking RTL through synthesis and timing closure; ability to interpret SDC, STA reports, and synthesis QoR summaries.
• Strong written communication skills; able to produce uArch specs and design review material independently.
• Experience with memory compiler toolchains.

Nice-to-have / preferred qualifications:

• Prior RTL ownership of a dataflow engine, NPU, or streaming DSP with token-based producer-consumer management.
• Experience co-designing with compiler or graph-optimization teams and familiarity with graph IR.
• Familiarity with NVM controller RTL (MRAM, RRAM), ECC, and weight storage use cases.
• Experience with IoT-class power budgets (sub-10 mW active, sub-100 µW standby).
• Familiarity with functional safety standards (ISO 26262, IEC 61508) as applied to execution fabric.
• Exposure to AI framework graph formats (ONNX, TFLite) and mapping graphs to hardware primitives.
• Tape-out credits on edge-AI, IoT, or wearable SoCs at 12nm or below.
• Experience with formal verification of flow-control logic, deadlock freedom, or bus protocol compliance.

Education Requirements

Not specified.

About the Company

Company: Lumiere Systems

Engineering services firm specializing in semiconductor and ASIC design and verification for ARM-based SoCs. Engages in full verification lifecycle (UVM/SystemVerilog, formal, gate-level simulation) and collaborates with global verification teams and client partners.