Hardware & Silicon Validation Senior Principal Engineer

Job Title

Hardware & Silicon Validation Senior Principal Engineer

Role Summary

Lead end-to-end post-silicon and hardware validation for high-performance data center ASICs, SoCs, and platforms. The role owns validation strategy, test architecture, and execution from early bring-up through production qualification and customer deployment.

Experience Level

Senior-level. Typical experience guidance: 15+ years of related experience with a Bachelor's degree, or 10–12 years with a Master’s/PhD (see Education Requirements for details).

Responsibilities

Accountable for planning, executing, and delivering hardware and system validation across product cycles and customer engagements.

• Define and own validation architecture, test plans, coverage metrics, and sign-off criteria.
• Lead post-silicon bring-up, functional validation, stress and corner-case testing across PVT conditions.
• Lead board bring-up, system integration, link training, and protocol validation for PCIe, Ethernet, DDR and other interfaces.
• Perform root-cause analysis and coordinate corrective actions across SoC, PHY, firmware, and board domains.
• Serve as technical point of contact for customers during qualification, deployment, and post-release support.
• Run debug war rooms, produce technical reports and executive summaries, and deliver best-practice guidance.
• Train customers on protocols, validation workflows, and issue triage.
• Collaborate with SoC/ASIC, PHY, Firmware/Software, Diagnostics, System Architecture, Manufacturing/CM, Program Management, and Field teams.
• Align validation and risk-mitigation plans with program schedules and quality objectives.

Requirements

Must-have technical skills and experience for immediate contribution.

• Proven track record leading hardware or post-silicon validation for complex SoCs, ASICs, boards, or systems through multiple product cycles.
• Experience with production test development, manufacturing qualification, and failure analysis (FA/PA).
• Hands-on expertise validating high-speed interfaces such as DDR4/DDR5, HBM, PCIe, Ethernet, and SerDes.
• Solid understanding of SoC architecture, hardware–software interactions, and system-level dependencies.
• Experience validating designs to industry standards (JEDEC, PCI-SIG, IEEE) and internal specifications.
• Proficiency with lab equipment: oscilloscopes, logic analyzers, protocol analyzers, traffic generators, and power measurement tools.
• Prior customer-facing experience (field support, FAE, validation leadership) and strong customer communication skills.
• Demonstrated ability to define and own test planning, coverage definition, execution, and sign-off.
• Clear technical writing and presentation skills for lab reports and executive summaries.

Nice-to-have: experience with CXL, NVMe/SSD controllers, PAM4/NRZ signaling, D2D interconnects, and system/platform-level validation.

Education Requirements

Required: Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 15+ years of related professional experience, OR Master’s / PhD in Computer Science, Electrical Engineering, or a related field with 10–12 years of related professional experience. (The posting specifies these degree and years-of-experience combinations as the baseline.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.