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Formal Verification R&D Engineer

Synopsys
May 22, 2026
Full-time
On-site
Bengaluru, Karnataka, India
EDA Jobs, Level - Mid-Career

Job Title

Formal Verification R&D Engineer

Role Summary

Work on the Formality ECO R&D team to design, implement, and deliver core enhancements to ECO (Engineering Change Order) tooling used in chip design flows. The role focuses on improving patch quality, performance, memory usage, and reliability for production-grade ECO solutions.

The engineer will collaborate with R&D peers and customer-facing teams to diagnose customer issues, drive technical investigations, and implement robust fixes from design through delivery.

Experience Level

Mid-level. Typical background: Bachelor's + 5+ years relevant experience or Master's + 3+ years relevant experience (see Education Requirements for details).

Responsibilities

Primary responsibilities include hands-on development, maintenance, and technical leadership on ECO-related components.

  • Design and implement core enhancements to Formality ECO technology.
  • Maintain, debug, and optimize existing functionality for performance and memory efficiency.
  • Lead technical investigations and perform root-cause analysis on complex ECO issues.
  • Collaborate with R&D and customer support to translate customer problems into practical solutions.
  • Promote code quality, testing, and best practices to improve long-term product health.

Requirements

Must-have technical skills and experience; followed by concise nice-to-have items.

  • Must-have: Strong software development experience in C++ on UNIX/Linux platforms.
  • Must-have: Proficiency with data structures, algorithms, system design, and performance-critical code.
  • Must-have: Experience working with large, complex commercial code bases and EDA flows.
  • Must-have: Familiarity with scripting (Python, Tcl, Perl, shell) and modern developer workflows (Git).
  • Must-have: Effective communication and ability to engage in technical discussions with peers and customers.
  • Nice-to-have: Familiarity with HDL (Verilog/SystemVerilog) or willingness to learn.
  • Nice-to-have: Knowledge of Logic Equivalence Checking (LEC).
  • Nice-to-have: Experience with developer productivity tools and AI assistants (e.g., GitHub Copilot).

Education Requirements

Bachelor's degree in Electrical, Electronics, or Computer Science Engineering with 5+ years of relevant experience, or a Master's degree with 3+ years of relevant experience. (Degrees and fields specified in the source.)


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-05-10