Formal Verification R&D Engineer
Work on the Formality ECO R&D team to design, implement, and deliver core enhancements to ECO (Engineering Change Order) tooling used in chip design flows. The role focuses on improving patch quality, performance, memory usage, and reliability for production-grade ECO solutions.
The engineer will collaborate with R&D peers and customer-facing teams to diagnose customer issues, drive technical investigations, and implement robust fixes from design through delivery.
Mid-level. Typical background: Bachelor's + 5+ years relevant experience or Master's + 3+ years relevant experience (see Education Requirements for details).
Primary responsibilities include hands-on development, maintenance, and technical leadership on ECO-related components.
Must-have technical skills and experience; followed by concise nice-to-have items.
Bachelor's degree in Electrical, Electronics, or Computer Science Engineering with 5+ years of relevant experience, or a Master's degree with 3+ years of relevant experience. (Degrees and fields specified in the source.)
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
