Fabric Interconnect Design Verification Engineer

Job Title

Fabric Interconnect Design Verification Engineer

Role Summary

Join Microsoft Silicon within Compute Silicon & Manufacturing Engineering (CSME) to verify fabric interconnects and related IP for cloud infrastructure chips. The role focuses on developing UVM-based verification environments, running and debugging simulations, and collaborating with design and partner teams to deliver silicon-quality verification.

This position is an individual contributor role based in Raleigh with a 3 days/week in-office cadence and limited travel (<25%).

Experience Level

Entry-level / Early career — requires at least 2 years of pre-silicon subsystem or IP verification experience; other minimum experience combinations apply depending on degree (see Education Requirements).

Responsibilities

Primary responsibilities include planning and executing verification activities for fabric interconnects and related blocks.

• Own verification of complex flows at fabric-interconnect or block level.
• Define verification strategies and test plans in collaboration with design and partner teams.
• Develop UVM/SystemVerilog verification environments and test benches; run and debug simulations.
• Apply random-stimulus and coverage-driven techniques to find bugs and meet coverage goals.
• Improve verification efficiency through new methodologies, tooling, or automation.
• Apply generative AI techniques to support verification tasks and productivity.
• Coach and mentor junior engineers and share best practices across teams.

Requirements

Key technical and security requirements. Degree requirements are summarized separately under Education Requirements.

• Must-have: 2+ years of pre-silicon subsystem or IP verification experience; experience developing and running verification using UVM/SystemVerilog.
• Must-have: Experience creating test benches, checkers, stimulus, and performing coverage signoff.
• Must-have: Ability to meet Microsoft security screening and export-control access requirements (including the Microsoft Cloud Background Check and citizenship/residency verification as required).
• Must-have: Practical ability to debug simulation failures and drive issues to closure.
• Preferred: Experience with Coherent Hub Interface (CHI) and AMBA protocols and understanding of cache-coherency architectures and microarchitectures.
• Preferred: Experience across a full product cycle from definition to silicon, including test-plan development and coverage signoff.
• Preferred: Scripting or software skills in Python or similar languages for test automation and post-processing.
• Preferred: Prior use of generative AI to support engineering workflows.

Education Requirements

Degree or equivalent experience is required: acceptable credentials include Doctorate, Master’s, or Bachelor’s in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. The posting specifies degree-to-experience tradeoffs: Master's + 1+ year technical engineering experience OR Bachelor's + 2+ years technical engineering experience (and alternative preferred thresholds: Doctorate OR Master’s + 3+ years OR Bachelor’s + 5+ years), and generally allows equivalent practical experience in lieu of degrees.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.