DRAM Design Tech Layout Engineer

Job Title

DRAM Design Tech Layout Engineer

Role Summary

Translate schematics into mask-ready layout for DRAM products, producing block-level IP layouts and physical verification artifacts. Work within the DRAM Design Engineering Group and coordinate with design, CAD and process teams to meet tapeout and quality targets.

Role requires planning, execution and cross-site collaboration with global teams (India, Japan, US and other sites) to deliver layouts on schedule.

Experience Level

Mid-level — expects approximately 3+ years of relevant layout design experience.

Responsibilities

Key day-to-day responsibilities include:

• Design and develop IP and block-level layouts for DRAM chips.
• Perform layout verification (LVS, DRC, EM), quality checks and produce documentation.
• Deliver layouts on schedule with acceptable quality and manufacturability.
• Estimate area/time, plan schedules, delegate tasks and execute across multiple simultaneous projects.
• Guide and review sub-block layout work from junior engineers and provide technical direction.
• Present layout plans and detailed proposals for global review.
• Collaborate closely with circuit designers, CAD and process engineers to resolve layout-related issues.

Requirements

Must-have technical skills and experience; concise list of required and preferred items.

• Minimum 3+ years of layout design experience in advanced CMOS processes.
• Hands-on IP layout development and physical verification for complex designs according to specifications.
• Expertise in layout area and routing optimization, design rules, yield and reliability considerations.
• Solid understanding of layout fundamentals: electromigration, latch-up, coupling/crosstalk, IR-drop, parasitics, matching and shielding.
• Ability to assess layout effects on circuit performance (speed, capacitance, power, area) and address trade-offs.
• Proven problem-solving skills for area, power, performance and physical verification issues.
• Practical experience with Cadence Virtuoso (schematic and layout) and verification tools; experience with Mentor Calibre or equivalent for physical verification.
• Experience in device matching, parasitic extraction/analysis, electromigration and isolation techniques.
• Leadership, multitasking, teamwork and ability to mentor junior engineers.

Nice-to-have:

• Skill coding and layout automation experience.
• Strong verbal and written communication skills and self-motivation.

Education Requirements

BE/BTech or MTech in Electronics/VLSI Engineering is preferred; exceptional Diploma holders in electronic or VLSI engineering may be considered. Equivalent practical experience is accepted.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.