Director of Silicon Design for MEM/PCIE COE

Job Title

Director of Silicon Design for MEM/PCIE COE

Role Summary

Lead the RTL silicon design effort for PCIe/CXL and memory subsystems within Marvell's Center of Excellence (COE). The role coordinates architecture, RTL, verification, firmware, and silicon validation to deliver production-ready IP subsystems used across Marvell SoCs.

The director manages distributed RTL design teams, drives reuse and quality, and ensures predictable delivery and tape-out readiness for complex SoCs targeting data center and AI customers.

Experience Level

Senior; typically requires about 10–15 years of relevant professional experience.

Responsibilities

Deliver and scale RTL subsystem development, manage teams, and remove technical and program risks across multiple products.

• Define and scale RTL development processes and drive reuse across IP and SoC programs.
• Own end-to-end delivery and sign-off of PCIe/CXL and memory subsystem RTL design.
• Collaborate with architecture, design verification, firmware, SoC integration, and post-silicon validation teams to reduce downstream risk.
• Manage distributed RTL design teams; develop technical depth and future leaders.
• Accountable for schedules, risk assessment, physical-design convergence, and tape-out readiness communication to senior management.
• Review and resolve cross-program technical issues and escalations.
• Engage with ecosystem partners (standards bodies, IP vendors, PHY providers) on interoperability and enablement.

Requirements

Key technical and leadership qualifications required for successful performance in this role.

• Must-have: Proven experience delivering complex PCIe/CXL and/or memory subsystems from architecture through RTL closure.
• Must-have: Strong SystemVerilog RTL development experience, physical-design convergence, power and performance optimization, and silicon bring-up.
• Must-have: Experience with EDA verification and debugging tools, scripting (Python or Perl), and revision control systems.
• Must-have: Strong communication, teamwork, attention to detail, and independent problem-solving skills.
• Must-have: Deep understanding of PCIe/CXL architectures and memory technologies (DDR, LPDDR, HBM).
• Must-have: Proven track record of leading distributed teams and owning complex subsystems end-to-end across multiple products.
• Nice-to-have: Experience engaging with standards bodies and IP/PHY vendors, and experience in a COE-style reusable IP organization.

Education Requirements

BS, MS, or PhD in Computer Science, Electrical Engineering, or Computer Engineering. The posting specifies approximately 10–15 years of relevant professional experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.