DFT Architect / Lead

Job Title

DFT Architect / Lead

Role Summary

The DFT Architect / Lead designs and deploys Design-for-Test architectures and leads DFT strategy for complex, high-performance SoCs. This role covers architectural definition, ATPG/MBIST/LBIST strategies, silicon bring-up and lifecycle management, and the automation of scalable DFT flows.

Works across RTL, synthesis, physical design, and validation teams to minimize test cost, meet coverage targets, and ensure smooth transition to high-volume manufacturing.

Experience Level

Senior — 7+ years of hands-on DFT experience, including multiple SoC tape-outs and first-silicon bring-up.

Responsibilities

Primary responsibilities include defining DFT architecture, optimizing test strategy, and leading silicon bring-up and debug.

• Define and own global DFT architecture: hierarchical scan, compressed ATPG, memory BIST/repair (BISR), logic BIST, and IEEE 1687 (IJTAG) for multi-die/chiplet designs.
• Develop defect-oriented test strategies and optimize pattern volumes for tester memory and test-time constraints.
• Integrate DFT requirements into RTL, synthesis, and physical design (STA/PD) flows and drive DFM initiatives to improve yield.
• Lead post-silicon validation, first-silicon bring-up, root-cause analysis, and debugging of ATE/system-level failures.
• Architect and maintain automated DFT flows using TCL, Python, or Perl; evaluate and benchmark EDA tools for advanced technology nodes (5nm/3nm+).
• Provide technical mentorship to engineering teams and consult on timing or routing issues introduced by DFT structures.
• Author comprehensive DFT specifications and strategy documents supporting project iterations.
• Own device execution when required: lead teams through spec, integration, verification, and silicon bring-up.
• Perform work in a safe and compliant manner supporting Environmental, Health, Safety & Security programs.

Requirements

Must-have technical skills and demonstrated experience required for the role; nice-to-have items listed separately.

• Must-have: 7+ years of hands-on DFT experience with multiple complex SoC tape-outs and proven silicon debug expertise (first-silicon bring-up, characterization, customer debug, ramp to production).
• Must-have: Expert proficiency with industry DFT EDA tools such as Synopsys TestMAX/DFTMAX, Cadence Modus, or Siemens/Mentor Tessent.
• Must-have: Deep knowledge of scan compression architectures, hierarchical DFT, and mixed-signal test integration.
• Must-have: Advanced scripting skills in TCL and Python or Perl to create CAD attributes and automate EDA flows.
• Must-have: Proven ability to resolve timing closure and complex ATPG coverage issues related to DFT.
• Nice-to-have: Experience with Automotive ASIL-D functional safety, In-System Test (IST), and periodic logic/memory monitoring.
• Nice-to-have: Knowledge of 2.5D/3D IC testing, TSV probing, or HBM test strategies.
• Nice-to-have: Experience with volume diagnostics, yield learning tools, and driving DPPM reduction; active participation in technical conferences or DFT patents.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field as stated by the employer.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.