Design for Test (DFT) Engineer

Job Title

Design for Test (DFT) Engineer

Role Summary

The DFT Engineer develops and implements testability solutions for complex digital ASICs, SoCs, and processors. The role partners with design, verification, and test teams to ensure products are designed for testability and that test-related issues are resolved throughout development.

Work takes place within a multidisciplinary R&D environment focused on high-reliability systems.

Experience Level

Mid-level. Typical experience: 5–7 years in ASIC/DFT engineering.

Responsibilities

Primary responsibilities include defining DFT architecture, implementing test solutions, and verifying testability across ASIC/SoC projects.

• Define and implement DFT architectures and test strategies for digital ASICs, SoCs, and processors.
• Perform testability analysis and generate test patterns.
• Develop and maintain DFT methodology and verification flows.
• Design and simulate circuits at the transistor level; evaluate hardware feasibility and optimize for performance, power, and cost.
• Contribute to system-level design and provide guidance for physical implementation, including floor-planning.
• Collaborate with design, verification, and test teams to resolve test-related issues.
• Document and teach best practices; mentor less experienced engineers.
• Support proposal and business development activities as needed.

Requirements

Must-have technical skills, experience, and constraints.

• Proven experience in DFT architecture, implementation, and verification for digital ASICs/SoCs.
• Experience with testability analysis and test pattern generation.
• Ability to design and simulate circuits at transistor level and contribute to physical/layout guidance.
• Strong analytical and problem-solving skills; attention to detail.
• Excellent written and verbal communication skills and ability to document detailed design specifications.
• Proven ability to lead or manage small technical teams and meet program deadlines.
• Ability to develop and teach engineering best practices and processes.
• Willingness and ability to obtain and maintain a U.S. government security clearance (required).

Education Requirements

Requires a Bachelor’s degree in Engineering or a related field; Master’s degree preferred. The posting specifies experience trade-offs by degree: 5–7 years with a Bachelor’s, 3–5 years with a Master’s, or 0–2 years with a PhD in ASIC Hardware Engineering or a related field.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.