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ASIC Verification Engineer

Capgemini
May 21, 2026
Full-time
Remote
Worldwide
$76,200 - $187,740 USD yearly
Verification Jobs, Level - Mid-Career

Job Title

ASIC Verification Engineer

Role Summary

Individual contributor role on the verification team responsible for functional quality of ASIC designs, with a strong focus on ARM-related IP (CPU Cortex‑A v9, GPU Mali, Debug: CSS600/CoreSight).

This position is 100% remote and involves owning verification activities across the project lifecycle and collaborating with global teams to improve verification methodology and design quality.

Experience Level

Mid-level — requires proven hands-on experience (typically 5+ years) in ASIC verification using modern methodologies.

Responsibilities

Primary responsibilities include:

  • Own and develop verification for core IP blocks (ARM CPU, GPU, debug blocks) as an individual contributor.
  • Perform specification reviews and produce verification plans and test cases.
  • Develop and maintain UVM/SystemVerilog environments and stimulus (including constraint‑random tests and assertions).
  • Perform coverage planning and analysis, debug failures, and run gate‑level simulations.
  • Design and implement C-based tests to configure and validate ARM IPs and reuse vendor test benches where applicable.
  • Collaborate with design teams to clarify requirements, share insights, and support debugging efforts.
  • Contribute to process improvements, verification methodology, and global team initiatives.

Requirements

Must-have and preferred skills:

  • Must-have: 5+ years hands-on ASIC verification experience with UVM/SystemVerilog, constraint‑random verification, assertions, coverage metrics and analysis, and gate‑level simulation.
  • Must-have: Strong familiarity with ARM IPs (Cortex‑A v9, Mali GPU, CSS600/CoreSight debug blocks).
  • Must-have: Experience writing C-based test cases to configure and test ARM IPs and reusing manufacturer test benches.
  • Nice-to-have: Experience creating UVM-based environments for block and subsystem-level verification.
  • Nice-to-have: Ability to read RTL (SystemVerilog, Verilog, VHDL); experience with revision control and CI/CD practices.
  • Nice-to-have: Strong documentation, process development, and cross-team communication skills.

Education Requirements

Not specified.

Base compensation range for the posted location: $76,200 to $187,740 per year.


About the Company

Company: Capgemini

Headquarters: Paris, France

Global consulting, technology and engineering services firm offering digital and business transformation, cloud, AI, and engineering/R&D services across industries. Employs around 340,000 people in 50+ countries and provides end-to-end solutions from strategy and design to engineering.

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Date Posted: 2026-05-21