ASIC Verification Engineer

Job Title

ASIC Verification Engineer

Role Summary

Capgemini Engineering seeks an ASIC Verification Engineer to own and execute verification activities for ARM-related IP blocks (CPU Cortex-A v9, Mali GPU, Debug — CSS600/CoreSight). This is an individual-contributor role focused on verifying block- and subsystem-level designs and improving verification practices across the global team.

This is a 100% remote position based in the posted location.

Experience Level

Mid-level — proven hands-on verification experience; posting requests approximately 5+ years of relevant experience.

Responsibilities

Primary responsibilities include planning, developing, executing, and improving verification for ASIC IP blocks and collaborating with cross-functional teams.

• Develop verification plans, test cases, and UVM environments for ARM-related IP blocks.
• Perform coverage analysis, assertion-based and constraint-random verification, and gate-level simulation.
• Debug RTL and testbench failures; lead root-cause analysis and issue resolution.
• Reuse and adapt vendor/manufacturer testbenches and C-based test cases to validate IP functionality.
• Participate in specification and design reviews; provide verification-driven feedback to improve requirements.
• Collaborate with global verification teams to standardize processes, tooling, and metrics.

Requirements

Must-have technical skills and experience; followed by concise nice-to-have items.

• Must-have: 5+ years of hands-on experience with modern verification methodologies (UVM/SystemVerilog), formal verification, constraint-random verification, assertions, coverage metrics and analysis, and gate-level simulation.
• Must-have: Strong working knowledge of ARM-related IPs (Cortex-A v9 CPU, Mali GPU, CSS600/CoreSight debug IP).
• Must-have: Experience designing and implementing C-based test cases to configure and exercise ARM IPs and reusing manufacturer-provided test benches.
• Nice-to-have: Experience creating UVM-based block-level environments reusable at subsystem level.
• Nice-to-have: Ability to read RTL (SystemVerilog/Verilog/VHDL), and experience with revision control and CI/CD workflows.
• Nice-to-have: Strong communication, documentation, and cross-team collaboration skills.

Education Requirements

Not specified.

About the Company

Company: Capgemini

Headquarters: Paris, France

Global consulting, technology and engineering services firm offering digital and business transformation, cloud, AI, and engineering/R&D services across industries. Employs around 340,000 people in 50+ countries and provides end-to-end solutions from strategy and design to engineering.