Analog Layout Engineer - AI/ML methodology

Job Title

Analog Layout Engineer - AI/ML methodology

Role Summary

The Analog Layout Engineer will create and verify physical layouts for analog integrated circuits and drive adoption of AI/ML-enabled layout tools and flows. The role sits on a small interdisciplinary team focused on accelerating analog layout development and improving parasitic prediction, device matching, and automation.

Experience Level

Mid-level. The role requests approximately 2–5 years of relevant experience.

Responsibilities

Key responsibilities include implementing, optimizing, and validating analog IC physical layouts and integrating AI/ML techniques into layout flows.

• Create custom analog IC layouts across multiple application areas (audio, imaging, high-speed, clocking, automotive, power management, etc.).
• Perform DRC/LVS verification and participate in post-layout simulation and sign-off activities.
• Apply layout techniques for device matching, symmetry, guard rings, shielding, and parasitic management.
• Manage parasitic extraction and collaborate with design engineers on post-layout simulations.
• Develop, test, and apply AI/ML-enabled tools to accelerate layout tasks, predict parasitics, optimize matching, and automate repetitive work.
• Drive adoption of new tools and flows across product teams and contribute ideas suitable for patents or publications.
• Work with advanced wafer processes and collaborate with cross-functional teams in a fast-paced environment.

Requirements

Minimum and preferred qualifications summarized. Degree and GPA details appear in the Education Requirements section below.

• Must-have: 2 to 5 years of relevant experience in analog layout or IC physical design.
• Preferred / Nice-to-have: strong fundamentals in analog layout concepts and hands-on layout project or internship experience with analog IPs (band-gap, ADC/DAC, amplifiers, oscillators, comparators, IO cells, LDO/DCDC).
• Familiarity with DRC/LVS, parasitic extraction, and EM/IR analysis.
• Working knowledge of Cadence Virtuoso Layout Suite and common verification tools.
• Foundational programming skills in Python and familiarity with libraries such as Pandas, PyTorch, TensorFlow, scikit-learn, or Matplotlib.
• Basic understanding of machine learning concepts (neural networks, graphs, clustering, regression, decision trees) and how they apply to layout automation.
• Strong verbal and written communication, analytical problem-solving, and ability to collaborate across time zones and functions.
• Demonstrated initiative and ability to drive results.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related field. The posting specifies a cumulative GPA of 3.0/4.0 or higher. (No mention of alternative degree-equivalent language or required advanced degrees.)

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.